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Schematic Editor
[Report No.] |
Description |
Workaround |
[SD 6144]
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When a macro to open a sheet is executed in the schematic sheet editor multiple times, the following error occurs in the "CR5000 Output Window". ERROR: bms-lib,bms-tool-tool-id: Bad state - ID not available >>>> * When the sheet editor is started from the Design File Manager, the file is closed when the editor is closed but the editor window remains and does not close. |
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[SD 6004]
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When the existing symbols and schematic sheets are saved in Rev.6.020 and later, the following phenomena may occur. It is possible this will occur when the existing data is abnormal data including DOS carriage return code. 1. On Symbol/Schematic editor -Two property viewers of the same property exist, and also the value is different from the set one. -When a schematic sheet is saved, an "36504 More than one net label has been assigned to net." error occurs. 2. With Circuit Rule Checker -Category 8:Net/Bus Mismatch , a "Illegal Net Label (plural name)" message is output. If you look in the Net/Bus Name" dialog, multiple net names have been set. |
A function to repair error data including DOS carriage return is added to Rev. 6.020. However, if error data cannot be repaired completely, these problems may occur. |
[SD 5507]
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When there is a signal line for which line width, line type and color are changed, and another signal line is connected to it in the way that a node is generated, the property information of the changed signal line in line width, line type and color is not reflected on the connected signal line. |
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[SD 5140]
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When you use [Edit]-[Copy to Clipboard]-[Rectangular Area] to cut out a part only and paste it into Word and then cancel grouping to edit lines, the sheet frame that you did not cut appears. Even though there are other objects in it, only the sheet frame appears additionally. |
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[SD 4504]
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In the "symbol pin editor" dialog, when the screen is scrolled during cell editing, the black cell under editing and the red cell that contains the cursor do not match. |
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[SD 4481]
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The specifications of "Components with Reference" that is one of the generation modes of "Sheet Reference Generator" seems strange. It is desired that other references be reassigned for the selected same reference resistance or capacitor. With respect to gates, regardless of generation mode it is desired for the same reference to be assigned for the same reference. |
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[SD 2725]
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When an existing symbol is deleted once and a differently shaped symbol of the same name is copied, the schematic data referencing the symbol is not changed to the new shape when it is opened. When you attempt to enter the symbol, it is the new shape while dragging but once it is placed, it is changes back to the original shape. |
The symbol is corrected by executing [Reload Symbol Figure]. |
[SD 1042]
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Using [Utilities]-[Net Utility]-[Generate Hierarchy Connector (Selecting Bus Case)], if a command is executed for the bus connected to a pin for which a pin name has not been input, changing of hierarchy connector references can be executed in the dialog but the changes are not reflected in the pin name. |
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Circuit Reference Allocator
[Report No.] |
Description |
Workaround |
[SD 6966]
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When the Circuit Reference Allocator is used for gate parts with the same reference that are located on multiple sheets and the "default power" and "default ground" sheet property values differ, the following error occurs and the reference is overwritten even though the pin numbers for the gate of the other sheets differ and there are no duplicates. <Mess.36218> Duplicate references have been allocated. References will be reallocated. References are reallocated even in "open gate" Execute mode. |
Default power and default ground values should be shared by all sheets. Use Power Box to indicate other power and ground values. If this is not possible, set the "Fixed Reference Designator" gate property on multiple sheets to "LOCKED". Use the Circuit Rule Checker to check for duplicated references and use the Circuit Reference Allocator only for checking to see if an error is generated, since some references may not have been locked. References are reallocated even in "open gate" Execute mode. |
[SD 2997]
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During hierarchical design, with regard to the gate at the second level, if power and ground symbols are connected to the common pins separately, the same reference does not occur and different references generated. |
Connect the power and ground symbol to the common pin using a series of net. Set the global net flag to ON in the Push Definition. |
Data Converter
[Report No.] |
Description |
Workaround |
[SD 3803]
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When LCDB->PMASTER (pma) (lcdb2pma.sh) is used, even though the pins of components that share pins other than VCC and GND in a different gate are the common terminal YES, a "PinNumber [XX] is duplicated" warning is issued and processing is skipped. |
On the PMASTER specifications, the common pins (other than power, ground, and NC) of different gates cannot be used. Even though .pma is output, error occurs with ggen and processing is skipped. Do not use the common pins of different gates for PWS operation. |
Circuit Data Backup
[Report No.] |
Description |
Workaround |
[SD 5813]
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Using the Circuit Data Backup, if you select "Used LCDB" for the target file, the LCDB directory is unexpectedly created for LCDBs that are not in use. Inside is pathname files only and LCDB is not created. |
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Electrical Net Editor
[Report No.] |
Description |
Workaround |
[SD 4781]
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In the Electrical Net Editor, E-net is processed automatically for a two-pin part. However, if one pin of the part is connected to the power or ground, the net of both ends of the part do not become the same E-net. |
Power and ground are not subject to E-net. |
Others
[Report No.] |
Description |
Workaround |
[SD 5206]
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When "%" is specified for Negative Logic Start Character and Negative Logic End Character, if you enter "%" on the schematic using [Draw] - [Text] or [Text form File], a bar is added to the string sandwiched by %, or, even though % is used independently, it is not displayed as it is entered (example: "%%%" is input but "%%" is displayed.) |
To display % as text, using two "%" characters for one "%" makes it possible to display "%" without a bar. Sometimes text strings with bar need to be entered in a schematic; Negative Logic Start Character is used for such setting. |
General
[Report No.] |
Description |
Workaround |
[SD 4494]
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With the dialog displayed, when a schematic sheet is clicked certain dialogs are hidden under the schematic sheet. |
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General
[Report No.] |
Description |
Workaround |
[AN 267]
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When both model name (asimModel) and constant (value) are defined for a component in a circuit, only the model name is output and the constant is not. |
Use a simulation value (asimValue). |
[AN 259]
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The parameter information (asimParamXX) set for the voltage current source and the circuit is not output. |
This is the specification as of Rev. 6.020. It is described in RevUP note items. |
[AN 247]
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For a schematic designed in hierarchy using SD, "Flat" is specified to output the net list. When property including "=" is set for a part in the level, if there is "," before or after that, the rest is not output. Example: When property R='3*v(out,in)' is set for R1, R1X1 aaa bbb R='3*v(out) is output. |
It is delimited because the bit end character has been set using ",". If "," is used for the property value use another character for the bit end character for landata.rsc. |
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